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ADV7403
PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Pixe l Port Pins P[19:0]
Data Sheet
Processor Mode
Format
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SDP
SDP
Video out, 8-bit, 4:2:2
Video out, 10-bit, 4:2:2
YcrCb[7:0] OUT
YcrCb[9:0] OUT
SDP
SDP
SDP
SDP
Video out, 16-bit, 4:2:2
Video out, 20-bit, 4:2:2
Video out, 24-bit, 4:4:4
Video out, 30-bit, 4:4:4
Y[7:0] OUT
Y[9:0] OUT
Y[7:0] OUT
Y[9:0] OUT
CrCb[7:0] OUT
CrCb[9:0] OUT
Cb[7:0] OUT
Cb[9:0] OUT
SM-SDP
CP
CP
Digital tuner input[1]
8-bit, 4:2:2, DDR
10-bit, 4:2:2, DDR
Output choices are the same as video out 16-/20-bit or pseudo 8-/10-bit DDR
D7 D6 D5 D4 D3 D2 D1 D0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CP
12-bit, 4:4:4, RGB DDR
D7 D6 D5 D4 D3 D2 D1 D0
D11
D10
D9
D8
CP
CP
CP
CP
Video out, 16-bit, 4:2:2
Video out, 20-bit, 4:2:2
Video out, 24-bit, 4:4:4
Video out, 30-bit, 4:4:4
CHA[7:0] OUT (for example, Y[7:0])
CHA[9:0] OUT (for example, Y[9:0])
CHA[7:0] OUT (for example, G[7:0])
CHA[9:0] OUT (for example, G[9:0])
CHB/C[7:0] OUT (for example, Cr/Cb[7:0])
CHB/C[9:0] OUT (for example, Cr/Cb[9:0])
CHB[7:0] OUT (for example, B[7:0])
CHB[9:0] OUT (for example, B[9:0])
SM-CP
HDMI receiver support,
CHA[7:0] OUT (for example, Y[7:0])
R[5:4] IN
CHB/C[7:0] OUT (for example, Cr/Cb[7:0])
R[1:0] IN
24-bit, 4:4:4 input
SM-CP
HDMI receiver support
CHA[7:0] OUT (for example, Y[7:0])
CHB/C[7:0] OUT (for example, Cr/Cb[7:0])
16-bit pass through
SM-CP
HDMI receiver support,
CHA[9:0] OUT (for example, Y[9:0])
CHB/C[9:0] OUT (for example, Cr/Cb[9:0])
20-bit, pass through
Rev. B | Page 16 of 20
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